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Macros</h2></td></tr>
<tr class="memitem:gaf3bdd7a21f9d6add3ec23802122a7a85"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#gaf3bdd7a21f9d6add3ec23802122a7a85">XZDma_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;<a class="el" href="group__zdma__v1__0.html#ga3218611d01dec526018a6bd63dce603c">XZDma_In32</a>((BaseAddress) + (u32)(RegOffset))</td></tr>
<tr class="separator:gaf3bdd7a21f9d6add3ec23802122a7a85"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1fe52ea6cc149bd35296d497837eff5b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga1fe52ea6cc149bd35296d497837eff5b">XZDma_WriteReg</a>(BaseAddress,  RegOffset,  Data)&#160;&#160;&#160;<a class="el" href="group__zdma__v1__0.html#ga35a6987a4645af9cf6fc7463ca90f855">XZDma_Out32</a>(((BaseAddress) + (u32)(RegOffset)), (u32)(Data))</td></tr>
<tr class="separator:ga1fe52ea6cc149bd35296d497837eff5b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Registers offsets</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Interrupt Enable/Disable/Mask/Status registers bit masks and shifts</div></td></tr>
<tr class="memitem:gaf2a5aa7481789b82f9a68ddbb803b072"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#gaf2a5aa7481789b82f9a68ddbb803b072">XZDMA_IXR_ERR_MASK</a>&#160;&#160;&#160;(0x00000BF9U)</td></tr>
<tr class="separator:gaf2a5aa7481789b82f9a68ddbb803b072"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Channel Control0 register bit masks and shifts</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Channel Control1 register bit masks and shifts</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Channel Peripheral register bit masks and shifts</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Channel Status register bit masks and shifts</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Channel Data Attribute register bit masks and shifts</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Channel DSCR Attribute register bit masks and shifts</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Channel Source/Destination Word0 register bit mask</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Channel Source/Destination Word1 register bit mask</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Channel Source/Destination Word2 register bit mask</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Channel Source/Destination Word3 register bit masks and shifts</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Channel Source/Destination start address or current payload</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>MSB register bit mask </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Channel Rate control count register bit mask</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Channel Source/Destination Interrupt account count register bit mask</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Channel debug register 0/1 bit mask</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Channel control2 register bit mask</div></td></tr>
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